LTC4268IDKD-1#PBF【PDF 34/46 页】IC PD HIGH POWER W/CNTRL 32-DFN

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LTC4268-1

42681fc

minimum on time along with synchronous rectification

sets the switch over to forced continuous mode operation.

The t

ON(MIN)

resistor is set with the following equation

tON(MIN)

( )

ON(MIN)

( )

104

1.063

Keep R

tON(MIN)

greater than 70k. A good starting value

is 160k.

Enable Delay Time (ENDLY)

Enable delay time provides a programmable delay between

turn-off of the primary gate drive node and the subsequent

enabling of the feedback amplifier. As discussed earlier, this

delay allows the feedback amplifier to ignore the leakage

inductance voltage spike on the primary side. The worst-case

leakage spike pulse width is at maximum load conditions.

So set the enable delay time at these conditions.

While the typical applications for this part use forced

continuous operation, it is conceivable that a secondary

side controller might cause discontinuous operation at

light loads. Under such conditions the amount of energy

stored in the transformer is small. The flyback waveform

becomes lazy and some time elapses before it indicates

the actual secondary output voltage. The enable delay time

should be made long enough to ignore the irrelevant

portion of the flyback waveform at light loads.

Even though the LTC4268-1 has a robust gate drive, the

gate transition time slows with very large MOSFETs. In-

crease delay time as required when using such MOSFETs.

The enable delay resistor is set with the following equation:

ENDLY

( )

ENDLY

( )30

2.616

Keep R

ENDLY

greater than 40k. A good starting point is 56k.

Primary Gate Delay Time (PGDLY)

Primary gate delay is the programmable time from the

turn-off of the synchronous MOSFET to the turn-on of

the primary side MOSFET. Correct setting eliminates

overlap between the primary side switch and secondary

side synchronous switch(es) and the subsequent current

spike in the transformer. This spike will cause additional

component stress and a loss in regulator efficiency.

The primary gate delay resistor is set with the following

equation:

PGDLY

( )

PGDLY

( )

+ 47

9.01

A good starting point is 27k.

Soft-Start Function

The LTC4268-1 contains an optional soft-start function that

is enabled by connecting an external capacitor between

the SFST pin and ground. Internal circuitry prevents the

control voltage at the V

CMP

pin from exceeding that on

the SFST pin. There is an initial pull-up circuit to quickly

bring the SFST voltage to approximately 0.8V. From there it

charges to approximately 2.8V with a 20礎 current source.

The SFST node is discharged to 0.8V when a fault occurs.

A fault occurs when V

is too low (undervoltage lockout),

current sense voltage is greater than 200mV or the ICs

thermal (over temperature) shutdown is tripped. When

SFST discharges, the V

CMP

node voltage is also pulled low

to below the minimum current voltage. Once discharged

and the fault removed, the SFST charges up again. In this

manner, switch currents are reduced and the stresses in

the converter are reduced during fault conditions.

The time it takes to fully charge soft-start is:

SFST

1.4V

20礎

=70kW C

SFST

礔

( )

applicaTions inForMaTion

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